In recent years there have been proposals of high-speed MOSFETs, MODFETs, and HEMTs employing, in the channel region, a strained Si (silicon) layer grown epitaxially on Si substrate with a SiGe (silicon-germanium) layer intervening. In a strained-Si FET, tensile stress arises in the Si layer due to the SiGe, which has larger lattice constants than does Si, and consequently the band structure in the Si changes, state degradation is removed, and carrier mobilities are increased. Hence by using such a strained Si layer as a channel region, operation can be made faster by a factor of 1.5 to 1.8 compared with normal devices. Moreover, normal Si substrate grown using the CZ method can be employed as the substrate, so that conventional CMOS processes can be employed to realize high-speed CMOS devices.
However, in order to achieve epitaxial growth of the desired strained Si layer described above as the channel region of a FET, a good-quality SiGe layer must be grown epitaxially on the Si substrate; but differences in the lattice constants of Si and SeGe have resulted in crystallinity-related problems such as dislocations. Consequently in the past there have been various proposals such as the following.
Methods which have been proposed include, for example, a method of using a buffer layer in which the Ge composition ratio of the SiGe is changed with a constant gradual gradient; a method of using a buffer layer in which the Ge (germanium) composition ratio is changed in steps (step-shape); a method of using a buffer layer in which the Ge composition ratio is changed in the manner of a superlattice; and a method in which a Si off-cut wafer is used, and a buffer layer is used in which the Ge composition ratio is changed with a constant gradient (Patent References 1 through 4).
The Patent References are as follows.    Patent Reference 1: U.S. Pat. No. 5,442,205    Patent Reference 2: U.S. Pat. No. 5,221,413    Patent Reference 3: International Patent No. 98/00857    Patent Reference 4: Japanese Patent Laid-open No. 6-252046
However, the following problems remain in the above-described technology of the prior art.
That is, the crystallinity of the SiGe deposited as a film using the above-described conventional techniques is in a poor state, with the threading dislocation density not reaching the level desired for devices. Furthermore, with respect to surface roughness which can cause defects when actually manufacturing a device, it has been difficult to obtain satisfactory substrates with a low dislocation density. The surface roughness is the consequence of the effect of irregularities, extending to the surface, which arise due to internal dislocations.
For example, when using a buffer layer in which the Ge composition ratio has a gradient, the threading dislocation density can be made comparatively low, but there is the problem that the surface roughness worsens; conversely, when using a buffer layer in which the Ge composition ratio is changed in a step-like fashion, the surface roughness can be made comparatively small, but there is the problem that the threading dislocation density increases. Furthermore, when an off-cut wafer is used, dislocations tend to emerge laterally rather than in the film thickness direction, but a sufficiently low dislocation density is not achieved.
Moreover, in processes to manufacture devices on a Si layer or similar deposited on a SiGe layer, various heat treatments are performed, and there is the problem that at this time the roughness at the surfaces and interfaces of the SiGe layer and Si layer is worsened.